28 lines
420 B
Plaintext
28 lines
420 B
Plaintext
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/**
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* Verilog Lexer
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*/
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module Foo(
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input logic Clk_CI,
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input logic Rst_RBI,
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input logic A,
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input logic B,
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output logic C
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);
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logic C_DN, C_DP;
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assign C = C_DP;
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always_comb begin : proc_next_state
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C_DN = A + B;
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end
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// Clocked process
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always_ff @(posedge Clk_CI, negedge Rst_RBI) begin
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if(~Rst_RBI) begin
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C_DP <= 1'b0;
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end else begin
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C_DP <= C_DN;
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end
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end
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endmodule
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